Semiconductor devices equipped with thin film transistors (TFTs) have been under development in recent years. Active matrix liquid crystal display devices and organic EL display devices and the like are major examples of such semiconductor devices. Those display devices have been used for various electronics including portable electronic devices such as cellular phones.
A number of thin film transistors (TFTs) are used as switching elements in display regions in active matrix display devices. TFTs are generally classified into amorphous silicon TFTs and crystalline silicon TFTs, depending on the crystallinity of the silicon thin films used. Because the field effect mobility in a crystalline silicon film is generally higher than that in an amorphous silicon film, crystalline silicon TFTs can operate faster than amorphous silicon TFTs. For this reason, by using a crystalline silicon film, not only TFTs provided as switching elements for each of the pixels (“pixel TFTs”) but also TFTs constituting the peripheral circuits such as driver circuits and various operational circuits disposed in the periphery of the display region (“driver circuit TFTs”) can be formed on the same substrate.
Recently, formation of photodiodes on the same substrate with pixel TFTs and driver circuit TFTs has been suggested for uses in display devices having photo sensor features, such as touchscreen display devices and display devices with ambient light sensors.
Here, pixel TFTs and driver circuit TFTs preferably have different structures, matched to their respective required properties.
The maximum allowable off-leakage current of pixel TFTs is very low. This is because in liquid crystal display devices, a voltage applied to liquid crystals needs to be maintained for one frame, until the display is refreshed, and a high OFF current (off-leakage current) of the pixel TFT causes the voltage applied to the liquid crystals to drop during this period of time, which can degrade the display properties.
A known structure of pixel TFTs is the structure having a Lightly Doped Drain region (herein after may be referred to as “LDD region”) disposed at least either between TFT's channel region and the source region or between the channel region and the drain region. Such structure is called “LDD structure.” In the TFT having this structure, the LDD region, which has a higher resistance than the source or drain region, is disposed between an edge of the gate electrode and the low-resistant source or drain region. Compared with a TFT without a LDD region (single drain structure), the TFT having the LDD structure can reduce the off-leakage current substantially. Moreover, with the LDD region, the electric field in the vicinity of the drain becomes less concentrated and thus, hot-electron-induced degradation can be suppressed. “Hot-electron-induced degradation” refers to a fluctuation in the transistor properties caused when a portion of hot electrons generated by the electric field concentration in the vicinity of the drain enter into the gate insulating film, and/or create a defect levels in the silicon film. Only a portion of the LDD region may overlap the gate electrode, and from this a similar effect can be obtained. One drawback of the LDD-structured TFT is that the LDD region becomes a resistor, which makes the current drive power lower than that of the single-drain TFT.
On the other hand, since the driver circuit TFT is required to operate at a high speed, the driver circuit TFT needs a high current drive power, that is, a high ON current.
One known structure of a driver circuit TFT is a structure in which the LDD region overlaps the gate electrode. This structure is called a “GOLD (Gate Overlapped LDD) structure.” When a voltage is applied to the gate electrode on a GOLD-structured TFT, electrons that will become carriers are accumulated in the LDD region that overlaps the gate electrode. This lowers the resistance of the LDD region, minimizing the reduction in the TFT's current drive power. Since this structure can also lower the impurity concentration in the LDD region more than the aforementioned TFT of LDD structure (the structure in which at least a portion of the LDD region does not overlap the gate electrode), the electric field concentration near the drain can be more effectively moderated, and therefore the hot electron degradation resistance is substantially improved.
However, the GOLD-structured TFT has a drawback of a higher off-leakage current than the aforementioned LDD-structured TFT, which makes the GOLD-structured TFT unsuitable to be used as a pixel TFT. This drawback is considered to be a result of the formation of an accumulation layer in the LDD region that overlaps the gate electrode even when the TFT is in the OFF state.
Therefore, for each TFT application and purpose of the use, the most appropriate TFT structure needs to be selected. That is, for example, in manufacturing an active matrix substrate in which a driver circuit is integrated, the pixel TFT and driver circuit TFT, whose structures are different from each other, need to be formed on the same substrate.
Patent Document 1 discloses a method of forming a driver circuit TFT and a pixel TFT on the same substrate. With this method, after forming on the substrate a plurality of semiconductor layers that are destined to become active layers for the driver circuit TFT and pixel TFT, first, impurity ion implantation for formation of an LDD region is conducted using a resist mask (this is called the first low-concentration impurity implantation), which is targeted only to the semiconductor layer that is destined to become the active layer for the driver circuit TFT. With this method, a gate electrode is formed on each semiconductor layer after the first low-concentration impurity implantation. Next, impurity ion implantation for formation of an LDD region is performed on the semiconductor layer that is destined to become the active layer for the pixel TFT (the second low-concentration impurity implantation) using the gate electrode as a mask. Then, high-concentration impurity ion implantation is performed to the semiconductor layers that are destined to become the active layers for the driver circuit TFT and pixel TFT, to form source and drain regions. In this way, the pixel TFT having LDD structure and the driver circuit TFT having GOLD structure are formed.
According to the method disclosed in Patent Document 1, the low-concentration impurity implantation is performed before and after the formation of the gate electrodes. This means that the method requires additional manufacturing steps, and therefore, leads to a higher production cost, compared with the case in which multiple TFTs having the same structure are formed.
In order to reduce the number of manufacturing steps and lower the production cost, and to increase productivity, it is important to reduce the number of photomasks used for producing the TFTs, even by just one. Photomasks are used in photolithography to form resist patterns that will become masks for etching or ion implantation. Therefore, one additional photomask means additional etching or ion implantation, as well as additional steps of forming resist patterns in photolithography, removing the resist pattern, and washing and drying. Resist pattern formation by lithography, in particular, involves many cumbersome steps including resist application, pre-baking, exposure, development and post-baking. One additional photomask, therefore, is accompanied by additional manufacturing steps, resulting in increased production cost, longer required lead time, and significantly decreased productivity.
For this reason, various processes for reducing the number of photomasks, even by just one, have been proposed (Patent Documents 2 through 5).
For example, with the methods proposed in Patent Documents 2 and 5, a double-layered gate electrode is formed on the semiconductor layer. Using the gate electrode as a mask, a high-concentration impurity implantation is performed on the semiconductor layer to form the source/drain regions. Then, only the top layer of the gate electrode is etched to narrow the width. Next, using the narrowed width top layer of the gate electrode as a mask and through the bottom layer, the low-concentration impurity implantation is conducted on the semiconductor layer to form an LDD region. With this method, a GOLD-structured TFT can be formed using a single photomask. Patent Document 3 proposes a method in which a double-layered gate electrode, with a wider bottom layer and a narrower top layer, is formed on each of the plurality of semiconductor layers on the substrate, and the LDD-structured TFT and the GOLD-structured TFT are formed separately, utilizing this structure of the gate electrodes.
Patent Document 6 discloses a method in which a resist mask is formed on each of the semiconductor layers that are destined to become active layers for GOLD-structured TFT and LDD-structured TFT respectively, to cover regions destined to become the channel regions, followed by the low-concentration impurity ion implantation. In this method, after the low-concentration impurity ion implantation is conducted, the aforementioned resist mask is removed. Then, a gate electrode that is somewhat larger than the removed resist mask is formed on the semiconductor layer that is destined to become the active layer for the GOLD-structured TFT. Also, on a semiconductor layer that is destined to become the active layer for the LDD-structured TFT, a gate electrode, which is the same size as the removed resist mask, is formed to cover the portion that is destined to become the channel region. Next, a mask is formed on the semiconductor layer that is destined to become the active layer for the LDD-structured TFT to cover the region to be preserved as the LDD region. Then, the high-concentration impurity ion implantation is conducted on these semiconductor layers to form the source/drain regions. This method eliminates the need to repeat the low-concentration impurity ion implantation twice as in the method of Patent Document 1.